VHDL modeling for digital design synthesis
Κύριος συγγραφέας: | |
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Μορφή: | Βιβλίο |
Γλώσσα: | English |
Έκδοση: |
Kluwer Academic
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Έκδοση: | 3rd pr. |
MARC
LEADER | 00000nam a2200000 i 4500 | ||
---|---|---|---|
001 | 1/12987 | ||
010 | |a 0-7923-9597-2 | ||
035 | |l 10001754 | ||
100 | |a 19981005d1998 0grey0105 ba | ||
101 | 0 | |a eng | |
200 | 1 | |a VHDL modeling for digital design synthesis |f by Yu-Chin Hsu ... [et al.] | |
205 | |a 3rd pr. | ||
210 | |a Boston |c Kluwer Academic |d 1998 | ||
215 | |a xvii,356 p. |c fig. |d 25 cm | ||
320 | |a Includes bibliographical references and index | ||
606 | 0 | |a VHDL (Computer Hardware Discription Language) | |
606 | 0 | |a Ηλεκτρονικοί ψηφιακοί υπολογιστές |x Σχέδιο και κατασκευή | |
676 | |a 621.392 | ||
701 | 1 | |a Hsu |b Yu - Chin |f 1958- | |
709 | |a Kluwer Academic | ||
801 | 0 | |a GR |b ΠΑ.Δ.Α. Βιβλιοθήκη Πανεπιστημιούπολης 2 |g AACR2 | |
852 | |a INST |b LIBRARY |e 19990105 |h 621.392 VHD |p 000007612 |q 000007612 |t BK |y 23 |z 1 | ||
901 | |a 000435 | ||
909 | |b 011993 | ||
970 | |a ΑΔΑΜ |b ΚΥΡΙΑΚΗ |z 1998-10 |
Εγγραφή στο Ευρετήριο Αναζήτησης
_version_ | 1780545235571441665 |
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author | Hsu Yu - Chin 1958- |
author_facet | Hsu Yu - Chin 1958- |
author_role | |
author_sort | Hsu Yu - Chin 1958- |
author_variant | h y - c hy-c |
building | Campus Library II |
collection | LIB2 Catalog |
dewey-full | 621.392 |
dewey-hundreds | 600 |
dewey-ones | 621 |
dewey-raw | 621.392 |
dewey-search | 621.392 |
dewey-sort | 3621.392 |
dewey-tens | 620 |
edition | 3rd pr. |
format | Book |
fullrecord | {"leader":"00993nam a2200265 i 4500","fields":[{"001":"1/12987"},{"010":{"subfields":[{"a":"0-7923-9597-2"}],"ind1":" ","ind2":" "}},{"035":{"subfields":[{"l":"10001754"}],"ind1":" ","ind2":" "}},{"100":{"subfields":[{"a":"19981005d1998 0grey0105 ba"}],"ind1":" ","ind2":" "}},{"101":{"subfields":[{"a":"eng"}],"ind1":"0","ind2":" "}},{"200":{"subfields":[{"a":"VHDL modeling for digital design synthesis"},{"f":"by Yu-Chin Hsu ... [et al.]"}],"ind1":"1","ind2":" "}},{"205":{"subfields":[{"a":"3rd pr."}],"ind1":" ","ind2":" "}},{"210":{"subfields":[{"a":"Boston"},{"c":"Kluwer Academic"},{"d":"1998"}],"ind1":" ","ind2":" "}},{"215":{"subfields":[{"a":"xvii,356 p."},{"c":"fig."},{"d":"25 cm"}],"ind1":" ","ind2":" "}},{"320":{"subfields":[{"a":"Includes bibliographical references and index"}],"ind1":" ","ind2":" "}},{"606":{"subfields":[{"a":"VHDL (Computer Hardware Discription Language)"}],"ind1":"0","ind2":" "}},{"606":{"subfields":[{"a":"\u0397\u03bb\u03b5\u03ba\u03c4\u03c1\u03bf\u03bd\u03b9\u03ba\u03bf\u03af \u03c8\u03b7\u03c6\u03b9\u03b1\u03ba\u03bf\u03af \u03c5\u03c0\u03bf\u03bb\u03bf\u03b3\u03b9\u03c3\u03c4\u03ad\u03c2"},{"x":"\u03a3\u03c7\u03ad\u03b4\u03b9\u03bf \u03ba\u03b1\u03b9 \u03ba\u03b1\u03c4\u03b1\u03c3\u03ba\u03b5\u03c5\u03ae"}],"ind1":"0","ind2":" "}},{"676":{"subfields":[{"a":"621.392"}],"ind1":" ","ind2":" "}},{"701":{"subfields":[{"a":"Hsu"},{"b":"Yu - Chin"},{"f":"1958-"}],"ind1":" ","ind2":"1"}},{"709":{"subfields":[{"a":"Kluwer Academic"}],"ind1":" ","ind2":" "}},{"801":{"subfields":[{"a":"GR"},{"b":"\u03a0\u0391.\u0394.\u0391. \u0392\u03b9\u03b2\u03bb\u03b9\u03bf\u03b8\u03ae\u03ba\u03b7 \u03a0\u03b1\u03bd\u03b5\u03c0\u03b9\u03c3\u03c4\u03b7\u03bc\u03b9\u03bf\u03cd\u03c0\u03bf\u03bb\u03b7\u03c2 2"},{"g":"AACR2"}],"ind1":" ","ind2":"0"}},{"852":{"subfields":[{"a":"INST"},{"b":"LIBRARY"},{"e":"19990105"},{"h":"621.392 VHD"},{"p":"000007612"},{"q":"000007612"},{"t":"BK"},{"y":"23"},{"z":"1"}],"ind1":" ","ind2":" "}},{"901":{"subfields":[{"a":"000435"}],"ind1":" ","ind2":" "}},{"909":{"subfields":[{"b":"011993"}],"ind1":" ","ind2":" "}},{"970":{"subfields":[{"a":"\u0391\u0394\u0391\u039c"},{"b":"\u039a\u03a5\u03a1\u0399\u0391\u039a\u0397"},{"z":"1998-10"}],"ind1":" ","ind2":" "}}]}
|
id | lib2_1/12987 |
illustrated | Illustrated |
institution | University of West Attica |
isbn | 0-7923-9597-2 |
language | English |
physical | xvii,356 p. fig. 25 cm |
publishDate | 1998 |
publisher | Kluwer Academic |
record_format | marc |
spelling | 19981005d1998 0grey0105 ba eng VHDL modeling for digital design synthesis by Yu-Chin Hsu ... [et al.] 3rd pr. Boston Kluwer Academic 1998 xvii,356 p. fig. 25 cm Includes bibliographical references and index VHDL (Computer Hardware Discription Language) Ηλεκτρονικοί ψηφιακοί υπολογιστές Σχέδιο και κατασκευή 621.392 Hsu Yu - Chin 1958- Kluwer Academic GR ΠΑ.Δ.Α. Βιβλιοθήκη Πανεπιστημιούπολης 2 AACR2 INST LIBRARY 19990105 621.392 VHD 000007612 000007612 BK 23 1 |
spellingShingle | Hsu Yu - Chin 1958- VHDL modeling for digital design synthesis VHDL (Computer Hardware Discription Language) Ηλεκτρονικοί ψηφιακοί υπολογιστές Σχέδιο και κατασκευή |
title | VHDL modeling for digital design synthesis |
title_auth | VHDL modeling for digital design synthesis |
title_full | VHDL modeling for digital design synthesis by Yu-Chin Hsu ... [et al.] |
title_fullStr | VHDL modeling for digital design synthesis by Yu-Chin Hsu ... [et al.] |
title_full_unstemmed | VHDL modeling for digital design synthesis by Yu-Chin Hsu ... [et al.] |
title_short | VHDL modeling for digital design synthesis |
topic | VHDL (Computer Hardware Discription Language) Ηλεκτρονικοί ψηφιακοί υπολογιστές Σχέδιο και κατασκευή |
topic_facet | VHDL (Computer Hardware Discription Language) Ηλεκτρονικοί ψηφιακοί υπολογιστές Σχέδιο και κατασκευή |